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Dzar's avatar
Dzar
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Solved

Reading HPS EMAC counters not reliable

UPDATE: Seems EMAC1 is looking OK. The problem, there, was understanding what's meant by "good" in some cases. But EMAC0 looks like it's almost not counting anything. It's quite sporadic when I see a...
  • Dzar's avatar
    Dzar
    7 years ago

    Final answer... Set the PR bit, not the RA bit. One does not need both, but the PR bit is the correct one if one wants counters to work. No documentation on this, sadly, but that's what we've deduced.

FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hello,

We were looking at the Synopsys Errata in case there is a known issue for this counter. One interesting thing that might affect the counters.

Operate the RxFIFO in the store-and-forward mode.

Operation_Mode Register: located at address:

0xFF701018 (for EMAC0)

0xFF703018 (for EMAC1)

Set bit 25 (“rsf” bit) to 0x1.

We looked at this register in the uboot that we are using in the system, and it is NOT set. It might be needed to be set before we can read from the counters.

I will test this and let you know the result.

Thanks