Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorreading external signal
Hi,
I need capture external signal (RGMII). I'm able to do it, but I have a problem when the clock is delayed (only a little) after the data. In that case I'm not able capture data corectly. In altera document AN477 is written: "the FPGA and HardCopy ASIC must shift the clock as necessary to capture the data. You can achieve this with a DLL and by assigning RX_CLK to a DQS pin or promoting RX_CLK to a global or regional net if you need a small clock latency." My question is how... How can I initialize DLL in Cyclone device (Cyclone III od IV) is there something like DLL? How can I propagate RX_CLK through regional net? Thanks2 Replies
Altera_ForumIn this context DLL = PLL
Refer to the infomation about PLL and ALTPLL megafunction provided in the same document- Altera_Forum--- Quote Start --- In this context DLL = PLL Refer to the infomation about PLL and ALTPLL megafunction provided in the same document --- Quote End --- Ok, when I don't use PLL I has to be able to set input delay for clock or data by the assignment editor or by the TimeQuest. I've tried to set "Input delay from pin to input register" at the data pins and it helps me but I don't understand what means the number in value column (assignment editor). Has somebody more experiences in this?
