Read pipelining in AXI-4 interfaces

The document you referenced seems to apply to M20K and MLAB memory applications, and doesn't mention HBM2; the AXI-4 interface for HBM2 includes the ID field, which exists specifically to support out-of-order transactions. From the AXI-4 standard:

The AXI4 protocol supports an extended ordering model based on the use of the AXI ID transaction identifier. See
Chapter A6 AXI4 Ordering Model.

But that is not really what I was asking about, which was support of pipelined reads (and writes); I do hope that pipelined reads are supported, because otherwise burst read transactions could be pretty slow (the latency between read address and returned data would be dead time).

After thinking about this for a while I realize that knowledge of the read pipeline depth is unnecessary, as the slave can just stop responding to read address transactions once it hits the pipeline depth limit.