Honored Contributorread from scfifo wrong!
my fist read data should be 40h,but now is 00h. left picture is from ALERA ,right picture is from my singalTapII, whether phase position has some problem?
Honored Contributori dont know ,hope some proficient help you.
Honored Contributoryour read data is 40h(signaltap), it is readout after rdreq pulse, so what is the problem?
Honored Contributormy fist read data should be 40h,but now is 00h.(the data read out is prior!)
Honored ContributorWhat settings did you use when you instantiated the scfifo?
Your results look consistent. You need to put rdreq at 1 before the rising edge of your clock. In your case the rdreq is taken in account one cycle after your green line.Honored ContributorThe results look correct to me too. rdreq is not asserted for the clock pulse under the green bar, but on the next clock edge (when rdreq is asserted) 0x40 comes out of the FIFO.
