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Altera_Forum
Honored Contributor
16 years agoThe results look correct to me too. rdreq is not asserted for the clock pulse under the green bar, but on the next clock edge (when rdreq is asserted) 0x40 comes out of the FIFO.
The results look correct to me too. rdreq is not asserted for the clock pulse under the green bar, but on the next clock edge (when rdreq is asserted) 0x40 comes out of the FIFO.