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DavidSmoot's avatar
DavidSmoot
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8 months ago

Read flash attached to Max II in Parallel Flash Configuration on legacy system

I have a customer requesting that I reverse engineer the firmware on a legacy system so he can program some older blank stock for spares. No available source code. No available schematics. The ...
Programmable Logic Device
FvM's avatar
FvM
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8 months ago

Hi,

sounds like an implementation of Parallel Flash Loader IP, if so it regularly supports "examine" (readback command) in Quartus programmer which would dump flash content to a .pof file. (Your question 1). There's also an option to read flash with special JTAG tools by using MAX II BSDL functionality.

2. No

3. Which chips? You are talking about 1 flash device. If talking about FPGA, what do you want to find out? If you have access to JTAG ports, BSDL allows to trace pin connections.

4. There's no readback of internal volatile FPGA configuration.

The configuration of your system isn't yet completely clear.
- JTAG configuration. Your post sounds like each chip (MAXII, bothd FPGAs) has separate JTAG port?

- configuration scheme. PFL IP supports boths PS (passive serial) and FPP (fast passive parallel) configuration. Do you know what is implemented?