Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)

Hi,

checked phasedone timing in real hardware with MAX10, PLL block is basically identical to Cyclone III/IV and 10.

See pulsewidth of phasedone varying with fvco/fscanclk ratio. Between 0.65*tscanclk for ratio 24 (fscanclk=50 MHz, fvco=1200 MHz) and up to 1.6*tscanclk for ratio 3 (fscanclk = 100 MHz, fvco=300 MHz). 300 MHz is beyond specification but still locking. 

Means step rate of 1/4 fscanclk can be always safely achieved. Even step rate of 1/3 fscanclk works with phasedone pulse > 1*tscanclk. Apparently the requirement to await phasedone rising edge before setting phasestep isn't strict.

Phasedone rising edge shows a certain jitter against scanclk, showing that it's actually asynchronous, timed by vco.

Regards
Frank