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YY's avatar
YY
Icon for New Contributor rankNew Contributor
4 days ago

Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)

Hello, Please tell me the maximum time between the execution of Phasestep and the completion of Phasedone. The relevant link is below. Cyclone® IV Device Handbook - Chapter 5: Clock Networks and P...
Programmable Logic Device
FvM's avatar
FvM
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1 day ago

Hi,
I can't answer the question officially. I see in simulation, that for the given parameters (fvco = 21*inclk0, scanclk = inclk0), a phase step can be performed every 3 scanclk cycles. I'm not waiting for phasedone = 0 but setting phasestep for two scanclk cycles.

Regards
Frank