MinzhiWang
Occasional Contributor
Occasional ContributorThe regisers EN port issue
Hello guys, There is one long regiser array implemented in my project, as following imgae: Every register is realized to latch its closed ALUT output. The FF primitive is called to implement...
Hi,
the problem might be explained by Cyclone 10 GX device handbook, Figure 7. ALM Connection Details for Intel Cyclone 10 GX Devices
It shows that clock selection (and also clock enable selection, because clock and enable are tied) for adjacent registers isn't independent. There are two muxes for four registers.Regards
Frank
