Forum Discussion
tedh4ddv
Occasional Contributor
Occasional Contributormultiple sof fpga configuration files stored in single flash
I gather that two or more .sof files may be combined to a single .jic file and written to an active serial flash device using the Serial Flash Loader IP core. I am not clear on how the fpga can be t...
tedh4ddvOccasional Contributor
Occasional ContributorCurrently the design provides the processor access to the serial configuration flash device via a SPI Flash Loader Platform (SPISlaveToAvalonMasterBridge and SPI_flash_platform_sfl_av_bridge). To utilize the Remote Update IP Core, I think the SPI_flash_platform_sfl_av_bridge should be removed, and the Remote Update IP Core would connect to the SPISlaveToAvalonMasterBridge via an Avalon MM interconnect. Does this sound reasonable?
