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Rodo's avatar
Rodo
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

MAX10, Nios 2: Intel FPGA Avalon I2C (Master) example ?

Is there a complete example (with buffer connections) of using this IP core in a nios system? I added the IP core to nios and generated the tri-state buffers with the GPIO Lite core but now I'm los...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi Rodo,

There are no examples available for this. What i can suggest is you have to make port interconnection between buffer module added and top module. Make sure the .qip file added as well. Below attached a simple example to show you the port interconnection between sub-module and top module.

Thanks,

Best regards,
Sheng

Rodo's avatar
Rodo
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Thanks but I got that part from a reply (comment) to my post at stackoverflow. How to instantiate in verilog : https://stackoverflow.com/questions/20066850/verilog-how-to-instantiate-a-module . It would be more helpful if the example you provided used the actual names for the intel i2c ip core. Curious, why you guys can offer this example but not a complete one? Are there any licensing issues? Thanks anyway.