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Steve9's avatar
Steve9
Icon for New Contributor rankNew Contributor
1 day ago

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy

Hi,    1. The Agliex 7 F Series EMIF User Guide  page 191 Figure 145 of section 6.5.6.3 shows RESET line to DRAM pulled up to VDD with 4.7k ohm resistor and this was implemented on Agilex 7 F serie...
Programmable Logic Device
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
6 hours ago

Hi Steve9 ,

 

"Can Altera explain why they recommend pullup which seems to be opposite of what memory vendor specifies?"

The power need to apply to reset_n pin at power-up sequence as mention in datasheet.

 

"why the eval board implementation for this signal termination does not match the EMIF user guide figure 143 recommendation?"

There are multiple termination scheme that has been used to terminate the clk signal. You can also terminate the signal to VDD. Also can terminate to both VDD and GND.

I think the board designer should identify which termination scheme that suitable for their board.

 

Regards,

Adzim