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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?

Hello, Using a PCIe IP in Root Port on a AGILEX 5, I have to use the GTS Reset Sequencer Intel FPGA IP configured in PCIe. With Quartus 2025.1, the i_refclk_bus_out port appears on the GTS Reset Se...
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hi @Serge93 ,

I open up the .qar that you provided it seen like the previous one with verilog code
And I do not seeing any .qsys file from there, please let me know if I miss it anywhere else.

"I tried to generate a project using Platform Designer instead directly in VHDL code and I got the same error.

Then I use the https://github.com/altera-fpga/agilex5-ed-pcie-rp/releases/tag/25.1-1 project.

This project is a nightmare to just take the GTS PCIe IP.

I deleted everything except the GTS PCIe IP and finally I got the same error of bus size."

>> Is the latest project provided by you on top_stm_1d_1q_25_1_0_129.qar is the design modified from the Github design ?

Last things to clarified
This is just a part of my design, I will connect the PCIe IP in Root Port to my NVMe Host IP.
>> is the design work well ONLY with GTS Reset sequence and the PCIe IP ?
>> I think you might need to connect with the rest right ?

If you think the communication here is bit slow, we can have a Teams call , I am based in GMT +8 Time zone, we can set a time where both of us is available.

Regards,
Wincent_Altera

Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

Hello Wincent,

So, I sent you my design which is done without qsys, only with VHDL files.

I did not sent you the design from https://github.com/altera-fpga/agilex5-ed-pcie-rp/releases/tag/25.1-1 project and on which I removed nearly everything becasue this is non sens.

So, the idea is the Altera IP expert analyze my design to see what is missing to avoid the bus error.

>> is the design work well ONLY with GTS Reset sequence and the PCIe IP ?
>> I think you might need to connect with the rest right ?

I do not understand this questions.

The goal is to provide me an instanciation of a GTS AXI Streaming PCIe IP on AGILEX 5 I can compile without errors.

Yes we can organize a Team call, I am based in Paris, France.

I am available Thursday an Friday morning of this week.

Please send me a link.

Thanks for help.

Serge

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi Serge,

    I will sent a the invitation link to you via your register email in this forum
    Time will be 10AM Paris , France Time Friday.
    Let me know if you did not received it. Looking forward to talk to you later.

    Regards,
    Wincent_Altera

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi @Serge93 ,

    I try to build a rootport design with some IO IP attach to it to ensure that the function is well.
    The compilation pass successful, I attach the .qar file there.
    Please refer, if you need more time to look at that we can reschedule our meeting.


    Regards,

    Wincent_Altera