Forum Discussion

atex-tester's avatar
atex-tester
Icon for New Contributor rankNew Contributor
5 days ago

Agilex 5 A5EC065BB32AE5SR0 issue

Hello  I built a new board with A5EC065BB32AE5SR0 , I got a issue with the fabric.  the FPGA is configurable, and Init done goes to high after configuration . I have a very simple verilog code wit...
Programmable Logic Device
atex-tester's avatar
atex-tester
Icon for New Contributor rankNew Contributor
4 days ago

 The led pin is gpio only.nothing is there and test point only.  The nios clk is 100mhz, I am using oscilloscope to capture the wave form. A constant one is shown only. Pin assignment is correct. The pll locked is high but nothing came out from the pin 

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 days ago

You'll have to use pll clock source with low jitter check this link

Schematic can be downloaded from installer package link

For example premium dev kit, I set the location as below:

 

 

Signal tap result:

I use issp to toggle the reset:

issp u0 (
.source (sys_reset)  //  output,  width = 1, sources.source
);