Forum Discussion
Occasional ContributorAGIB027R29A1E2VC suppoprts LPO?
Regular ContributorLooking at the available documentation for the AGIB027R29A1E2VC (Agilex 7 I-Series), I don't have specific LPO (Linear Pre-drive Output / Local Oscillator, or Linear-drive Pluggable Optics — whichever you mean) support details in the sources available to me.
What I can confirm about this device's transceiver configuration:
It carries 64 F-Tile FGT transceiver channels, 8 F-Tile FHT transceiver channels, and an R-Tile PCIe/CXL controller, with 32 CXL lanes. https://docs.altera.com/r/docs/683458/current/agilextm-7-fpgas-and-socs-device-overview/agilextm-7-fpgas-and-socs-f-series
The transceivers support data rates up to 58 Gbps. Agilex™ 7 FPGAs and SoCs Device Overview
The Agilex 7 I-Series uses F-Tile and R-Tile transceiver types (E-Tile and P-Tile are not present in this series). Agilex™ 7 FPGAs and SoCs Device Overview
However, LPO (Linear Pluggable Optics) support — which involves specific transceiver analog output drive characteristics and DSP bypass modes — is not explicitly documented in the sources I have available for this part. This is a nuanced transceiver feature that depends on F-Tile analog drive capability details.
I'd recommend checking the Agilex 7 F-Tile Transceiver PHY User Guide and the Agilex 7 F-Series and I-Series Known Issue List directly on the Altera documentation portal for the most current LPO support status, as this is the kind of feature that may also be subject to silicon revision constraints. Note also that Agilex 7 production devices manufactured before 2024 had FHT transceiver EOJ performance limitations, with devices manufactured in 2024 and beyond being fully compliant with published specifications Agilex™ 7 F-Series and I-Series Known Issue List — so silicon date code can matter for high-speed transceiver features.
Occasional ContributorHi, thanks for sharing the information.
I had another question, could you help confirm the exact FPGA or FPGA board that is described here
- Farabi_Altera
Hi, Looking at what's documented in the available sources, I can confirm the following about the 400G DR4 LPO demonstration on Agilex 7:
The demonstration is an interop demo implementing a **4x 100G design transmitting 400GbE traffic with 100G-DR4 LPO modules**, targeting Agilex 7 FPGAs and SoCs. Agilex™ 7 FPGAs and SoC FPGAs
For the specific hardware platform used in that type of testing, the **Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile)** — part number **AGIB027R31B1E1V** — is the documented hardware used for testing, along with an FMCA module for loopback. Triple-Speed Ethernet Intel Agilex™® 7 FPGA IP Design Example User Guide
On the transceiver tile side, the Agilex 7 I-Series uses F-Tile transceivers Agilex™ 7 FPGAs and SoCs Device Overview , and the Agilex 7 F-Tile supports a wide range of optical modules including XFP, QSFP-DD, OSFP, QSFP/QSFP28, QSFP56, SFP+, SFP28, SFP56, and CFP/CFP2/CFP4. Agilex™ 7 FPGAs and SoCs Device Overview
Regarding the media mode requirement for this type of design: for F-Tile FGT transceiver designs above 50G PAM4 using 400G optical modules for loopback, adaptation will fail unless the media mode is set to VSR/Optics. The workaround is to use the `set_media_mode` process in `ttk_helper_fgt_eth.tcl` to set media mode to VSR/Optics, following register-level steps for logical channels 0–15. This issue is fixed starting with **Quartus Prime Pro Edition Software version 22.3**. Why doesn’t my link come up when I use a 400G optical module in my Intel Agilex® 7 FPGA I-Series F-tile design?
So in summary: the FPGA board is the **Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile), AGIB027R31B1E1V**, running a 4×100G F-Tile FGT design with 100G-DR4 LPO modules to achieve 400GbE.
