rdreq didnt read all the data in dcFIFO (functional simulation)

ok.noted.

now, i have another issue when combining my sub blocks (datapath + CU).

when i simulated the datapath block separately, data is read out nicely in 4 clock cycles at every rising edge during rdreq is HIGH. but, now, when i tested in combined block with CU, it's failed. FYI, rdreq(read_fifo) is not controlled by CU. i control it manually. this CU is responsible for write operation(which is successful simulated). rdreq depends on "Routerclk" and writereq(write_fifo) depends on "clk".

i attached the simulation for combined design + FBD + successful simulation for Non combined design.

As u can see in the encapunitsimulation picture, the data is written to FIFO(during write_fifo is HIGH). FOUR 16-bit data is written to FIFO(i put the number in pink color). but, when rdreq is HIGH(read_fifo is HIGH), it's missed the last data, which is 0000000000000000. encapunitsimulation2 shows weird counting of the data in fifo.

i want the data to be read out as in simulationnoncombined picture.

(functional test simulation).

Please help.

Thanks Guru..