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so how does Quartus fix timing violations caused by clock skew? (sorry, I'm an ASIC guy where adding delay buffers is how you fix hold vios).
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Basically, it will try and move the registers around, and maybe try a different routing.
There are no buffers in FPGAs. Unlike Asics - generates clocks in FPGAs are a bad idea. they can have massive skew on them as the routing is not up to scratch. Clock enables are the much prefered/recommended method
In the olden days, designers used to use LUTs to delay signals to account for skew or delay. AHDL even has an LCELL function that would insert an extra LUT for you at the HDL level. But as chips clocked faster, this trick became less reliable as the effects of temperature , placement and routing had a much greater effect on the delay than the LUTs themselves, so you have no reliable way to delay a signal enough.
So, in FPGA land, the only way to fix hold violations is to make the route shorter. Easiest way to make the gap shorter is to reduce the logic between registers. Or when it comes to DSPs or RAMs, add extra pipelining. It's quite common when you get to the limits of the chip fmax, you can only have 1 or 2 luts between registers, and even then as the chip gets full, extra pipeline states are required to account for the routing delay and congestion around the chip.
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