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Altera_Forum
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12 years ago

Random single hold violations on Arria V design that doesn't push timing or util. ???

Hi - I have a design that uses about 20% of the FPGA Fabric on an ArriaVSoc. I've added my own logic to the GHRD. It doesn't push timing (my logic is 100MHz or less), or utilization (see above, eve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

what do you mean by "delay"? The code is synthesised into logic. Registers need to be added at the code level otherwise the code behaviour would not match the hardware.