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Altera_Forum
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11 years ago

Random single hold violations on Arria V design that doesn't push timing or util. ???

Hi - I have a design that uses about 20% of the FPGA Fabric on an ArriaVSoc. I've added my own logic to the GHRD. It doesn't push timing (my logic is 100MHz or less), or utilization (see above, eve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It can, but not if the DSP blocks are too far apart. It doesnt have much scope to move them. The easiest way to make life easier is put an extra register between the DSPs in the source code, it means the path wont be so long and quartus has much greater scope to move them. Alternatively, use regions to lock specific DSPs in certain areas.