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Altera_Forum
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12 years ago

Random single hold violations on Arria V design that doesn't push timing or util. ???

Hi - I have a design that uses about 20% of the FPGA Fabric on an ArriaVSoc. I've added my own logic to the GHRD. It doesn't push timing (my logic is 100MHz or less), or utilization (see above, eve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

ACTUALLY - I think I found the common thread. these are all DSP-block to DSP-block paths. In the original design, the customer was short on DSP blocks so I forced it to build gate multipliers, I removed that constraint for this revision. Trying it now with the constraint back in place.

Can't Quartus resolve hold vios between dsp blocks?

/j