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Altera_Forum
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11 years ago

Random single hold violations on Arria V design that doesn't push timing or util. ???

Hi - I have a design that uses about 20% of the FPGA Fabric on an ArriaVSoc. I've added my own logic to the GHRD. It doesn't push timing (my logic is 100MHz or less), or utilization (see above, eve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Check the start and end points - do they make sense?

In a previous version of Quartus I have seen it merge registers in two different entities, creating violations in two bits of logic that should have no relation to each other. I had to specific that auto-shift register recognition was turned off for these two entites - it broke the connection and removed the timing violations.