Random single hold violations on Arria V design that doesn't push timing or util. ???

Thanks Tricky. My design contains

a) the ArriaV SoC Golden Reference Design

b) some new logic I generated

c) a block I designed last year that has been built many dozens of times and ships in a customers' product.(albeit on a Stratix IV)

I get hold violations, consistently, very deep in block c) in a simple multi-bit shift register on a single clock domain. (so very little logic between registers) Quartus just appears to be unwilling (or unable?) to insert delay between two sequential registers. If remove a significant amount of logic from the total design (like 1/2 of b) ) the issues go away.

it's just weird.... I know how to fix setup vios, and cross-clock-domain stuff, but not hold vios deep in a single clock domain - except by adding buffers.

/j