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Altera_Forum
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11 years ago

Random single hold violations on Arria V design that doesn't push timing or util. ???

Hi - I have a design that uses about 20% of the FPGA Fabric on an ArriaVSoc. I've added my own logic to the GHRD. It doesn't push timing (my logic is 100MHz or less), or utilization (see above, eve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Have you analysed the hold timing? is it always in the same block? how many layers of logic are there between the registers where the hold violation occurs. If you are getting it 50% of the time that suggests poor logic design, even with 100MHz clock.

If it's failing in the same place, how about posting the code where the design fails on timing?