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Altera_Forum
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11 years ago

Ramp generation through HSMC DAC Stratix III using DSP Builder

I am able to generate proper ramp signal in DSP Builder simulink but when I program it into the FPGA, the output signal through the HSMC DAC is saturating. What is causing this and how to remove this...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I tried for 10 kHz, the output did look like a ramp but actually that too was saturated. I could not get any solution for this. Using an analog ramp generator circuit is the only solution for now.