Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Ramp generation through HSMC DAC Stratix III using DSP Builder

I am able to generate proper ramp signal in DSP Builder simulink but when I program it into the FPGA, the output signal through the HSMC DAC is saturating. What is causing this and how to remove this...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Given that it is probably the transformer causing this, there is no way to correct it short of generating an arbitrary signal which is predistored so that when it goes through the transformer it distorts back into the correct signal. But I'm not entirely sure how you would go about calculating that.