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Altera_Forum
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11 years ago

Ramp generation through HSMC DAC Stratix III using DSP Builder

I am able to generate proper ramp signal in DSP Builder simulink but when I program it into the FPGA, the output signal through the HSMC DAC is saturating. What is causing this and how to remove this...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I am trying to generate 100 Hz ramp signal that is quite low for the board but even if I try the same for higher frequencies like 10 KHz it shows the same saturation although the generated frequency is correct.In case of sine wave of 10 kHz and higher, the output signal is perfect.