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Altera_Forum
Honored Contributor
Honored ContributorRamp generation through HSMC DAC Stratix III using DSP Builder
I am able to generate proper ramp signal in DSP Builder simulink but when I program it into the FPGA, the output signal through the HSMC DAC is saturating. What is causing this and how to remove this...
Altera_ForumHonored Contributor
Honored ContributorWhat you may be seeing is the effect of that transformer - assuming you are using the Terasic ADA board, I used that in a project at Uni a couple of years ago and the transformer basically just distorted signals at both low frequencies and high frequencies.
Have you tried other waveforms and frequencies?
