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Honored Contributor
Honored Contributorrace: enable vs. clk in a FF
Hello, Once again me with a dummie question. Is about the correct way to manage the enable signal of a Flip Flop in VHDL. If the generation of the signal enable is managed with the...
Altera_ForumHonored Contributor
Honored ContributorFvM is correct. From your description it sounded to me like you were generating the enable signal from the same clock domain as the data but not using the clock itself as the enable.
However, TimeQuest should perform clock-as-data analysis if you were using the clock as an enable signal.
