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Altera_Forum
Honored Contributor
Honored Contributorrace: enable vs. clk in a FF
Hello, Once again me with a dummie question. Is about the correct way to manage the enable signal of a Flip Flop in VHDL. If the generation of the signal enable is managed with the...
Altera_ForumHonored Contributor
Honored ContributorThe problem would arise, if you use an edge aligned PLL clock itself as enable signal. A clock enable usually is the output from another FF. So it's perfectly delayed to act as an enable for the next clock edge. The timing analyzer and timing driven place and route has only to maintain this natural register timing.
