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Altera_Forum's avatar
Altera_Forum
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16 years ago

race: enable vs. clk in a FF

Hello, Once again me with a dummie question. Is about the correct way to manage the enable signal of a Flip Flop in VHDL. If the generation of the signal enable is managed with the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You don't have to worry about it at all. Both the enable and the data input to the flip flop are treated as part of the data path when it comes to timing analysis. You should control both with the same clock edge. The timing analyzer and fitter will take care of the rest.

Jake