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Altera_Forum's avatar
Altera_Forum
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16 years ago

race: enable vs. clk in a FF

Hello,

Once again me with a dummie question.

Is about the correct way to manage the enable signal of a Flip Flop in VHDL.

If the generation of the signal enable is managed with the same clock of the FLIP FLOP that this signal is going to control, how I know which one arrives first?

Do I must manage the generation of the enable with the falling edge and then the flip flops that receives this signal with the rising edge?.

Quartus reports this kind of conditions?

Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You don't have to worry about it at all. Both the enable and the data input to the flip flop are treated as part of the data path when it comes to timing analysis. You should control both with the same clock edge. The timing analyzer and fitter will take care of the rest.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The problem would arise, if you use an edge aligned PLL clock itself as enable signal. A clock enable usually is the output from another FF. So it's perfectly delayed to act as an enable for the next clock edge. The timing analyzer and timing driven place and route has only to maintain this natural register timing.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    FvM is correct. From your description it sounded to me like you were generating the enable signal from the same clock domain as the data but not using the clock itself as the enable.

    However, TimeQuest should perform clock-as-data analysis if you were using the clock as an enable signal.