R-Tile CXL IP Design Example simulation using Xcelium instead or VCS?

From "R-Tile Intel® FPGA IP for Compute Express Link* (CXL) Design Example User Guide" ID: 723223, the simulation specifies Synopsys VCS, can Cadence Xcelium be used in place? The IP libraries can be generated for Xcelium but can the test bench be modified to run on Xcelium as well?