R-Tile Avalon Streaming PIPE Direct x16: Locks COM(K28.5) Symbols correctly but some lanes do not.

Hello Wincent,

Thank you for the reply.

Yes, I am using the x16 configuration, and all 16 lanes are occupied. After the reset release sequence, the link proceeds to Polling.Active and Polling.Configuration on all 16 lanes. However, the problem is that the lanes that receive consecutive TS1/TS2 correctly are not stable. The set of “good” lanes changes every time I reboot the server with the FPGA card installed. In other words, the behavior looks very random.

So to answer your questions:

• Yes, I am using all 16 lanes.
• It is not only lane 8 and lane 9. The lanes that work and the lanes that fail change after each reboot.
• At the moment, I am testing only in Gen1. This issue is currently being observed during Gen1 link training. After this is solved, my first goal is to bring the link to L0 and then speed up to Gen4.

For the PIPE Direct configuration, I am using:

• PIPE Direct 16-channel
• 1x16, Octet 0 - 8 lane, Octet 1 - 8lane
• Gen4 configuration, currently down-training and debugging in Gen1

Regarding your question about reset sequence or speed change:

At the moment, I am focusing on the reset sequence path.

I already built an RTL simulation environment and connected my soft IP in the same way as in hardware. In RTL simulation, the reset sequence itself appears to complete normally without any issue.

However, in SignalTap, I sometimes see unrealistic behavior, for example pin_perst_n_o continuing to toggle, possibly due to setup timing violations around the TX clock domain. Because of that, it is difficult to trust SignalTap captures for validating the reset sequence directly.

Do you have any recommendation for how to debug or validate the reset sequence in this situation, when SignalTap itself may be showing unreliable behavior due to timing issues?

I also have one additional question.

In the waveform shown in the following link:
PIPE Direct Reset Sequence

this is a Gen1 reset sequence, but even in Gen1, both ln0_pipe_direct_txdatavalid0_i and ln0_pipe_direct_txdatavalid1_i appear to go high.

However, in Figure 48, the PIPE Direct TX Data Path for Gen1 seems to show a format where only txdatavalid0 toggles.

Because of this, I am not fully sure which behavior should be considered correct during the reset sequence for Gen1.

Could you please clarify which one should be followed during Gen1 reset sequence?
Should I treat the reset-sequence waveform as the expected behavior, or should I follow the interpretation shown in Figure 48 for Gen1 TX datapath formatting?

Thank you again for your help.

Best regards,
Jayden