I'm building a Binary Game for my final project in Digital Logic and Design and a small portion of this game I'm building uses a countdown timer to show how much time you have left in your round. I hooked up a clock to my output and got it running, counting down 1 second at a time. Then I hooked up a second clock (same clock but I changed the clock divider by a factor of 10) to my other output and was wanting to have it countdown in 10 second intervals. And it does countdown in 10 second intervals the issue is that it counts down at the wrong time. The 10 second countdown is triggered on the 5 sec of the 1 sec. clock countdown. So I get 99.98.98.97.96.85.84.83.82.81.80.89.88.87.86.75.74.73.72.71.70.79....and so on..... Any quick fixes? Or has anyone had this issue before? I'm a complete newbie so talk slow and use small words :-P

you need to align the two countings such that when counter1sec = 0 ~ 9 it aligns with counter10sec 0 for 10 clocks. If you are using two independent clocks you are likely to run into trouble. use fast clock as usual for both counters then use clockenable e.g. when counter1sec = 9 then count down the other counter.

Just using 1 clock going into 2 different clock dividers with different values

In that case all you need is to make sure your divided clocks are in phase. But to avoid the hassle I will run counter1sec on its clock starting from say 1000 at reset release. Then I will run counter10sec starting from say 100 after reset release on same clock but use the other 1/10 clock as clockenable to count down. Thus at start after reset release it should align like this: 1000 999 998 997 996 995 994 993 992 991 990 ... 100 100 100 100 100 100 100 100 100 100 99 ... and don't forget to keep clock enable under reset till release.

This is the clock divider that I'm using the only difference between my 2 clock dividers is the "integer :=25000000" in one and "integer :=250000" in the other...what exactly do I need to change to have them lined up? Thanks in advance for any help... LIBRARY ieee; USE ieee.std_logic_1164.all; ---------------------------------- ENTITY clk_div is generic(DIVISOR : integer := 25000000); port( clk: in std_logic; x: out std_logic ); END clk_div; ----------------------------------- ARCHITECTURE freq OF clk_div IS signal temp: std_logic := '0'; begin process(clk) variable counter: integer range 1 to DIVISOR; begin if(clk'event AND clk = '1') then if(counter = DIVISOR) then counter := 1; temp <= NOT temp; else counter := counter + 1; end if; end if; end process; x <= temp; END freq; -----------------------------------

The problem you have may be creating "ripple clocks". These are bad. A ripple clock is where you use registers in your design to act as a new clock. What you should be creating instead are clock enables. To create a clock enable structure try: PROCESS(reset, clock) BEGIN IF (reset = '1') THEN counter <= 0; clock_enable <= '0'; ELSIF (rising_edge(clock)) THEN IF (counter = counter_limit - 1) THEN clock_enable <= '1'; counter <= 0; ELSE clock_enable <= '0'; counter <= counter + 1; END IF; END IF; END PROCESS; Aside from that, your code to generate the count down behavior should probably make use of a good synchronous reset. Building a process with an asynchronous reset and a clock enable looks like this: PROCESS(reset, clock) BEGIN IF (reset = '1') THEN --put initial conditions here ELSIF (rising_edge(clock)) THEN IF (clock_enable = '1') THEN --put code here END IF; END IF; END PROCESS;

Quirk with my clocks | Altera Community

13 Replies

Altera_Forum
Honored Contributor
14 years ago
you need to align the two countings such that when counter1sec = 0 ~ 9 it aligns with counter10sec 0 for 10 clocks.
If you are using two independent clocks you are likely to run into trouble. use fast clock as usual for both counters then use clockenable e.g.
when counter1sec = 9 then count down the other counter.
Altera_Forum
Honored Contributor
14 years ago
Just using 1 clock going into 2 different clock dividers with different values
Altera_Forum
Honored Contributor
14 years ago
In that case all you need is to make sure your divided clocks are in phase. But to avoid the hassle I will run counter1sec on its clock starting from say 1000 at reset release. Then I will run counter10sec starting from say 100 after reset release on same clock but use the other 1/10 clock as clockenable to count down.
Thus at start after reset release it should align like this:
1000 999 998 997 996 995 994 993 992 991 990 ...
100 100 100 100 100 100 100 100 100 100 99 ...

and don't forget to keep clock enable under reset till release.
Altera_Forum
Honored Contributor
14 years ago
This is the clock divider that I'm using the only difference between my 2 clock dividers is the "integer :=25000000" in one and "integer :=250000" in the other...what exactly do I need to change to have them lined up?

Thanks in advance for any help...

LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------
ENTITY clk_div is
generic(DIVISOR : integer := 25000000);
port(
clk: in std_logic;
x: out std_logic
);
END clk_div;
-----------------------------------
ARCHITECTURE freq OF clk_div IS
signal temp: std_logic := '0';
begin
process(clk)
variable counter: integer range 1 to DIVISOR;
begin
if(clk'event AND clk = '1') then
if(counter = DIVISOR) then
counter := 1;
temp <= NOT temp;
else
counter := counter + 1;
end if;
end if;
end process;
x <= temp;

END freq;
-----------------------------------

Altera_Forum

Honored Contributor

14 years ago

The problem you have may be creating "ripple clocks". These are bad. A ripple clock is where you use registers in your design to act as a new clock. What you should be creating instead are clock enables.

To create a clock enable structure try:

PROCESS(reset, clock)
BEGIN
    IF (reset = '1') THEN
        counter <= 0;
        clock_enable <= '0';
    ELSIF (rising_edge(clock)) THEN
        IF (counter = counter_limit - 1) THEN
            clock_enable <= '1';
            counter <= 0;
        ELSE
            clock_enable <= '0';
            counter <= counter + 1;
        END IF;
    END IF;
END PROCESS;

Aside from that, your code to generate the count down behavior should probably make use of a good synchronous reset. Building a process with an asynchronous reset and a clock enable looks like this:

PROCESS(reset, clock)
BEGIN
    IF (reset = '1') THEN
        --put initial conditions here
    ELSIF (rising_edge(clock)) THEN
        IF (clock_enable = '1') THEN
          --put code here
        END IF;
    END IF;
END PROCESS;

Altera_Forum
Honored Contributor
14 years ago
I agree with Kosh about idea of clock enable but looking at your code:
1) Your counters will be aligned in simulation but for hardware you need reset.
2) I think you mean how to align output(x) from both at start. In that case invert temp at same value in either case. Or in fact just use one counter to get two outputs.
Altera_Forum
Honored Contributor
14 years ago
Alright well I've got the clocks working, but I have 2 more questions that hopefully somebody might be able to answer.

1) How would I go about implementing a reset for the clock? I've got it where the clock stops counting at 90 seconds and freezes...now I'd like to be able to hit a Key and reset the whole thing back to 00.

2) And I've been stuck on this one for a while...I had 8 switches each representing 8 bits of data...they sum together perfectly but whenever I add any other component to my project that has to do with a clock 3 of my 8 switches stop functioning. They begin to act like they are the negative value of what they actually are. The clock is in no way connected to the 8bitadders so I'm really not sure why there is an issue. I was going to ask my professor last week but he dipped out 2 days early for Thanksgiving and canceled all of his classes.
Altera_Forum
Honored Contributor
14 years ago
I'm not entirely sure on (1) without seeing how you have stopped the display at 90. One thing of note: if you are bringing in a button (or switch), be sure to sync it to your clock before using the signal to control anything. All it takes is one or two registers to properly sync it to the clock.

For (2), verify that your timequest timing analyzer report indicates you have no timing errors and no unconstrained paths. If you do have problems - fix these first. Also, it would be a good idea to add a register stage for your switches too. I won't go into detail unless you are interested.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
I'm not entirely sure on (1) without seeing how you have stopped the display at 90. One thing of note: if you are bringing in a button (or switch), be sure to sync it to your clock before using the signal to control anything. All it takes is one or two registers to properly sync it to the clock.

For (2), verify that your timequest timing analyzer report indicates you have no timing errors and no unconstrained paths. If you do have problems - fix these first. Also, it would be a good idea to add a register stage for your switches too. I won't go into detail unless you are interested.
--- Quote End ---

I probably stopped the clock the dumbest way possible but I'm a complete newbie when it comes to Quartus and most of the time the answers you guys give just fly right over my head.

To stop the clock I made the input for the 10's place (2nd digit) a 3 input and gate. The first input is the clock itself, the second input is the switch that turns the clock on and the 3rd input is where I took the output of the 2nd digit used the lpm_compare tool and said when the output equaled 9 to output a 0 which I inverted and tied back in to the beginning of the 3 input and.

As for (2) this is all I can really add, the adder works just great when its in its own project, but when I add a clock it stops working...even if I delete the clock back out and remove it from the project that adder still doesnt work then.

What's a register stage?
Altera_Forum
Honored Contributor
14 years ago
I can't say I've spent much time using the schematic entry for FPGA design. I generate most of my designs with VHDL.

In your case a register stage is a D flip-flop. It is basically used to delay signals by 1 clock or synchronize signals to your clock domain (area of your design running on a specific clock).

For (2), you should have a Timequest report show up in the report window of Quartus after you compile. I'm guessing that you have not generated a .sdc file to constrain your design. I would suggest searching a bit on the forums, I'm sure there is a guide to setup Timequest properly.

Forum Discussion

Quirk with my clocks

13 Replies

Recent Discussions

MAX 10. No 3.0 V Schmitt Trigger I/O standard

Agilex5 Engineering Silicon

Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?

Arria 10: Remote Update Watchdog unpredicted behavior

CYCLONE 10LP Decouple capacitors