Quirk with my clocks

I can't say I've spent much time using the schematic entry for FPGA design. I generate most of my designs with VHDL.

In your case a register stage is a D flip-flop. It is basically used to delay signals by 1 clock or synchronize signals to your clock domain (area of your design running on a specific clock).

For (2), you should have a Timequest report show up in the report window of Quartus after you compile. I'm guessing that you have not generated a .sdc file to constrain your design. I would suggest searching a bit on the forums, I'm sure there is a guide to setup Timequest properly.