Quirk with my clocks

This is the clock divider that I'm using the only difference between my 2 clock dividers is the "integer :=25000000" in one and "integer :=250000" in the other...what exactly do I need to change to have them lined up?

Thanks in advance for any help...

LIBRARY ieee;

USE ieee.std_logic_1164.all;

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ENTITY clk_div is

generic(DIVISOR : integer := 25000000);

port(

clk: in std_logic;

x: out std_logic

);

END clk_div;

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ARCHITECTURE freq OF clk_div IS

signal temp: std_logic := '0';

begin

process(clk)

variable counter: integer range 1 to DIVISOR;

begin

if(clk'event AND clk = '1') then

if(counter = DIVISOR) then

counter := 1;

temp <= NOT temp;

else

counter := counter + 1;

end if;

end if;

end process;

x <= temp;

END freq;

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