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eagles's avatar
eagles
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3 years ago
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Questions about RapidIO II IP core

Hello!

I am trying to use Rapidio II IP core to establish SRIO communication between FPGA and DSP. Here are some questions I have met:

Question 1

Are these signals used by users to transmit data packets?

Question 2

I notice that these signals belongs to an avalon-st sink. Should I create an avalon-st source by myself to send the data packets to him? If so, must this avalon-st source be created by Qsys or platform designer?

Question 3

The signal gen_tx_data is 128bits. Is the maximum bit width of a data packet only 128 bits?

4 Replies

  • Hi,


    Below is the answers for your questions:


    1. Yes, those are the Pass-Through Interface Signals
    2. The Avalon-ST pass-through interface is an optional interface that is generated when you select the Avalon-ST pass-through interface in the Transport and Maintenance page of the RapidIO II parameter editor.
    3. Yes, only 128 bits.


    For more details, please refer to Rapid IO II UG.

    https://www.intel.com/content/www/us/en/docs/programmable/683444/20-3/avalon-st-pass-through-interface-91575.html


    Regards,

    Pavee


  • Hi,


    Just wanted to check with you, is your concern has been addressed?

    If yes , kindly do let me know.

    Thank You


    Regards,

    Pavee


  • eagles's avatar
    eagles
    Icon for New Contributor rankNew Contributor

    Hi,

    My questions has already solved because of your answer. I've already accepted your solution.

    Thank you very much!

    Regards

  • Hi,


    I’m glad that your question has been addressed, I now transition this thread to community support.

    If you have a new question, feel free to open a new thread to get the support from Intel experts.

    Otherwise, the community users will continue to help you on this thread.

    Thank you.