eagles
New Contributor
3 years agoQuestions about RapidIO II IP core
Hello!
I am trying to use Rapidio II IP core to establish SRIO communication between FPGA and DSP. Here are some questions I have met:
Question 1
Are these signals used by users to transmit data packets?
Question 2
I notice that these signals belongs to an avalon-st sink. Should I create an avalon-st source by myself to send the data packets to him? If so, must this avalon-st source be created by Qsys or platform designer?
Question 3
The signal gen_tx_data is 128bits. Is the maximum bit width of a data packet only 128 bits?
Hi,
Below is the answers for your questions:
- Yes, those are the Pass-Through Interface Signals
- The Avalon-ST pass-through interface is an optional interface that is generated when you select the Avalon-ST pass-through interface in the Transport and Maintenance page of the RapidIO II parameter editor.
- Yes, only 128 bits.
For more details, please refer to Rapid IO II UG.
Regards,
Pavee