--- Quote Start ---
Hi,
if you want to stay with your old description you can use "Implement as Output of Logic Cell".
I have your design modified. You can use the Assignment Editor in order to make the assignments. You will find the editor under : Assignments -> Assignment editor.
You have to set the assignment to all outputs of your gates you would like to preserve.
Maybe wildcards could be used, but I'm not sure about that.
Kind regards
GPK
--- Quote End ---
Hi,
Thanks alot! But Im thinking it will be quite complicated if my design (similar pattern as the one I posted) are getting longer and complicated. Do you think is will be more wise to use components rather than functions?
Honored Contributor
