--- Quote Start ---
The reason for preventing this optimization, is that I want to see the real total number of gates utilized in the designs.
thanks for the advice. I think i should change to component instead of function
--- Quote End ---
Hi,
if you want to stay with your old description you can use "Implement as Output of Logic Cell".
I have your design modified. You can use the Assignment Editor in order to make the assignments. You will find the editor under : Assignments -> Assignment editor.
You have to set the assignment to all outputs of your gates you would like to preserve.
Maybe wildcards could be used, but I'm not sure about that.
Kind regards
GPK
Honored Contributor
