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Altera_Forum's avatar
Altera_Forum
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16 years ago

Question on LE

Dear all, Im wondering if it is possible to have a design that actually has fewer logic gates but took up more LE than another design that has more logic gates? This is happened to my desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Design A has 36AND 96XOR , consumed 82 LE, while

design B has 35AND 120XOR, consumed 79 LE

i think it will be odd to report a result as such in my work.

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Hi,

I assume that your gate are all 2-input gates. In an FPGA your logic is implemented in LUT.

The LUT has at least 4 input and one output. That means you can implement every logic function with 4 inputs and one output. The fitter will look for ways to fill the LUT's effectively. There is an Assignment (implement as output of logic cell) which could be used to force the Fitter to implement the outputs of the gate in one LUT (Implement as Output of Logic Cell).

I have a small example attached. Maybe this solves your problem.

Kind regards

GPK