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Altera_Forum's avatar
Altera_Forum
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13 years ago

Question about the VHDL sequential statements

Hi,

I just got some questions with the following processes when I design a simple MOD-9 counter for concept clarifications:

1. In program 1, the simulation result is actually counting from 0 to 10, not 0 to 9. Is that because "q <= q +1;" and "if (q = 10) then" block are Concurrently executed? Does that mean within the if..else... statement, the codes are also concurrently executed?

2. I understand that process 2 is not working fine because it is not synthesis-able, but why program 3 is working fine?

Thanks a lot!

Program 1:

---------------------------------------

process(clk,set,q)

begin

if reset='0' then

q <= 0;

elsif clk'event and clk='1' then

q <= q +1; -- this is a counter that counting from 0 to 10, but not 0 to 9.

if (q = 10) then -- want to avoid number 10 after q++, but it still has 10 shown up in the result.

q <=0;

end if;

end if;

end process;

---------------------------------------

Program 2:

---------------------------------------

process(clk,set,q)

begin

if (q = 10) then -- this is not synthesis-able. i understand it.

q <=0;

end if;

if reset='0' then

q <= 0;

elsif clk'event and clk='1' then

q <= q +1;

end if;

end process;

---------------------------------------

Program 3:

---------------------------------------

process(clk,set,q)

begin

if reset='0' then

q <= 0;

elsif clk'event and clk='1' then

q <= q +1;

end if;

if (q = 10) then -- but compared to program 2, why this code is working fine after i put the "if (q=10) then" part to the end of the process?

q <=0;

end if;

end process;

---------------------------------------

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Although you may see program 3 "working fine", it's not guaranteed to do. Depending on timing details, the counter may possibly count to 7 instead of 9. It's no correct synchronous description.

    Program 1 is the correct counter code, but you need to understand the clearly specified behaviour of sequential processes. All signals are updated after the end of the process. the comparison "if q = 10" (no brackets required in VHDL, by the way) "sees" the previous counter value, not the new one.

    The below style emphasizes the actual operation of the code more clearly, I think. 

    if q = 9 then 
  q <=0;
else
  q <= q + 1;
end if;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks a lot. Now I got the idea:

    If there are more than one assignments to the same signal value in sequential statements of one process. Only the last one will be effective.

    Thanks.

    --- Quote Start ---

    Although you may see program 3 "working fine", it's not guaranteed to do. Depending on timing details, the counter may possibly count to 7 instead of 9. It's no correct synchronous description.

    Program 1 is the correct counter code, but you need to understand the clearly specified behaviour of sequential processes. All signals are updated after the end of the process. the comparison "if q = 10" (no brackets required in VHDL, by the way) "sees" the previous counter value, not the new one.

    The below style emphasizes the actual operation of the code more clearly, I think. 

    if q = 9 then 
  q <=0;
else
  q <= q + 1;
end if;

    --- Quote End ---