Question about the VHDL sequential statements

Thanks a lot. Now I got the idea:

If there are more than one assignments to the same signal value in sequential statements of one process. Only the last one will be effective.

Thanks.

--- Quote Start ---

Although you may see program 3 "working fine", it's not guaranteed to do. Depending on timing details, the counter may possibly count to 7 instead of 9. It's no correct synchronous description.

Program 1 is the correct counter code, but you need to understand the clearly specified behaviour of sequential processes. All signals are updated after the end of the process. the comparison "if q = 10" (no brackets required in VHDL, by the way) "sees" the previous counter value, not the new one.

The below style emphasizes the actual operation of the code more clearly, I think.

if q = 9 then 
  q <=0;
else
  q <= q + 1;
end if;

--- Quote End ---