Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThank you all for your input on this.
I actually wasn't convinced on the half clock period min/max settings, the problem being that I can't know which clock would be used to synchronize the reset. The reset_path command doesn't seem to exist anymore, can't find it on any help or reference manual and google barely comes up with two forum posts (one of which is this one). In the end, I changed to SDC statement to the following which I believe does the trick:set_false_path -to
set_false_path -to If I'm not mistaken, this would only create a false path to the clear port of the register, thus keeping the path between sync and sync_rst. Regards, Sebastian.