Question about register's initial value

Hi,

You can set the Power-Up Level option for one or more registers. If registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous clear cannot power up to High. Similarly, if registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous preset cannot power up to Low. Note that Quartus Prime Integrated Synthesis reads default values for registered signals defined in VHDL code and converts the default values into Power-Up Level settings. The software also synthesizes variables that are assigned values in Verilog HDL initial blocks into power-up conditions.

You may refer to Chapter 1.5.1: Register Power-Up Values for details

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf

Thanks.

Best regards,

KhaiY