Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

question about propagation delay of basic logical gates in IC

Hi guys,

Is anybody know the delay for AND2, OR2, NOT and D flip-flop based on the popular fabrication technique? and suppose the delay for an AND2 gate is unit 1, what about the delay for AND3 or AND4 under the same fabrication? I am talking about the propagation delays of gates within an IC.Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Hi guys,

    Is anybody know the delay for AND2, OR2, NOT and D flip-flop based on the popular fabrication technique? and suppose the delay for an AND2 gate is unit 1, what about the delay for AND3 or AND4 under the same fabrication? I am talking about the propagation delays of gates within an IC.Thanks.

    --- Quote End ---

    The question has a different answer for every different type of technology.

    - The answer for a CPLD will be different than the answer for an FPGA which will be different than the answer for an ASIC

    - For a given technology, the answers can vary for different suppliers. For a given technology, the answer can vary by the process used by the same supplier to produce different generations of product

    Kevin Jennings
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    For FPGAs the delays for simple functions (ones that fit into a lookup table) should be similar. For example AND2 and OR2 fit within a single LUT and so the delay should be the same. The delay for AND3 and AND4 will be the same as AND2 because those functions (3 and 4 input) still fit within a LUT. The total delay is a result of the place and route too so there is no simple answer for that one.