Question...

You simply define regs array as a 'wire' intead of 'reg'.

Then you assign the actual register value to these signals.

Cris, can you please give me example...

reg [7:0] regA;

reg [7:0] regB;

reg [7:0] regC;

reg [7:0] regD;

what I need is to address different sets or regs with the same "name"... how to explain...

some variable regArr, an array (packed or unpacked - not sure), 3 elements, at different circumstances, should contain links to let's say {regA, regB, regC} or {regB, regC, regD}, and the same "code" do the following

regArr[1] <= 8'h44;

in first example regB will be assigned, in second - regC.

Is it achievable using simple (re-)assignments?

Do you mean the reg-array link rule is supposed to be changed during operation? Or do you select it at compile time?

In the first case you can't use simple fixed assignments, because these would infer a physical connection between register and signal. You'd rather use selective assignments with conditionals or case statements.

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In the first case you can't use simple fixed assignments, because these would infer a physical connection between register and signal. You'd rather use selective assignments with conditionals or case statements.

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Yes... I see, it is not possible. Thank you!

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You simply define regs array as a 'wire' intead of 'reg'.

Then you assign the actual register value to these signals.

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Or do you select it at compile time?

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Cris, can you give example please.

wire regArr[31:0];

assign regArr = { regA, regB, regC, regD };

Please excuse me if my questions seem stupid... I am completely lost in it.

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wire regArr[31:0];

assign regArr = { regA, regB, regC, regD };

Please excuse me if my questions seem stupid... I am completely lost in it.

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This way you define regArr as an array or 32 single bit wires

If you want a single 32bit wire vector you should write:

wire [31:0] regArr;

assign regArr = { regA, regB, regC, regD };

I'm not sure, but i think Quartus Verilog compiler also supports this syntax:

wire [7:0] regArr [0:3];

assign regArr[0] = regA;

assign regArr[1] = regB;

assign regArr[2] = regC;

assign regArr[3] = regD;

which is more similar to what you asked in the original post.

Please note that with this method you transfer registers data into regArr but you can't use

regArr as a register. Then the following operation is illegal

regArr[2][7:0] <= regArr[2][7:0] + 8'd1;

Cris, it seems we (also me) come to understanding what I mean and what I need. Let me explain again (because I probably was unclear before).

I need several (lets say 8) registers, for examle regA, regB, regC, regD, regE, regF, regG, regH.

Depending on the input data, for example regselect8[2:0], I need to be able to perform assignment and arithmetic operations on specific register through array, for example "regArr8[regselect8[2:0]][7:0] <= 0;" or "regArr8[regselect8[2:0]][7:0] <= regArr8[regselect8[2:0]][7:0] + 8'b1;" (exact syntax depends on organization of regArr).

At the same time, depending on other regselect16[1:0], I need to perform operations on pairs of registers regA:regB, regC:regD etc, for example "regArr16[regselect16[1:0]][15:0] <= regArr16[regselect16[1:0]][15:0] + 16'b1;"

All assignments will take place in same always block. If I put an analogy, it is a kind of implementation of x86 CPU, when you can address AL and AH registers but at the same time can address AX as a group of these registers.

Edit: or even better analogy: x86 has AH, AL, BH, BL, CH, CL, DH, DL, which individually can be addressed with 3 bits selector according to 8-bit access instruction bits. At the same time there're 16-bit access instructions, which address AX, BX, CX and DX (2 bits selector) but actually addresses these xH and xL registers, but in pairs.

As I suggested before, IMHO the best solution is using a case statement which selects the right registers pairs (and possibly the required operation) depending on regselect.

The operation:

regArr16[regselect16[1:0]][15:0] <= regArr16[regselect16[1:0]][15:0] + 16'b1;

Must be written extensively, something like this:

case(regselect16[1:0])

...

2'b00 :

begin

if (regA == 8'hFF)

regB <= regB + 8'h1;

regA <= regA + 8'h1;

end

2'b01 :

begin

if (regC == 8'hFF)

regD <= regD + 8'h1;

regC <= regC + 8'h1;

end

...

endcase

Remember that HDL is not a sequential programming language but a description of hardware behaviour. So, a register can be assigned only by a single process.

If I understood correctly and considering the example you posted, you can't assign the same physical register considering in one place regselect8 and in another regselect16: you must have a single process where all conditions must be evaluated and assignments must be made inside non overlapping cases.

Sorry I can't explain it in a clearer way right now. Maybe you can start writing some code and I would give advice.