Question...

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wire regArr[31:0];

assign regArr = { regA, regB, regC, regD };

Please excuse me if my questions seem stupid... I am completely lost in it.

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This way you define regArr as an array or 32 single bit wires

If you want a single 32bit wire vector you should write:

wire [31:0] regArr;

assign regArr = { regA, regB, regC, regD };

I'm not sure, but i think Quartus Verilog compiler also supports this syntax:

wire [7:0] regArr [0:3];

assign regArr[0] = regA;

assign regArr[1] = regB;

assign regArr[2] = regC;

assign regArr[3] = regD;

which is more similar to what you asked in the original post.

Please note that with this method you transfer registers data into regArr but you can't use

regArr as a register. Then the following operation is illegal

regArr[2][7:0] <= regArr[2][7:0] + 8'd1;