Occasional ContributorQuesiton for Cyclone IV EP4CE15M9I7N design
There are some questions I still did not get the answer.
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1) Bank 3 & 4 are used for DDR2 RAM. In each bank, there are two
reference pin VREFB3N0 & VREFB3N1. Just confirm only one pin should be
used as reference, the other one can be used as general IO, right ?
Answer -> Yes, one pin can be used as general IO. The usage depends upon which VREF group you are using.
XSHEN -> What do mean depends on VREF group? I think you are talking about VREF is referred to its bank, right?
2) In the pin out list, there is dedicated pin for DDR2 DQS and CLK.
Just confirm any diferential IO at banck 3 & 4 can be used for DDR2 DQS
and CLK, right?
Answer -> Though the dedicated DQS pin is optional to use, please note that this pin drive the dedicated phase shift ciruitry which helps in fine tuning of the input strobe.
XSHEN -> I did not get the answer. My question is that any specified pin for DQS and CLK from FPGA side?
4) I use high speed ADC with LVDS output based on power supply = 1.8V.
But intel sepc requires FPGA LVDS IO VCCIO = 2.5V. Can connect it
drectly? DC couple?
Answer -> Please refer to this KDB article: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...
XSHEN -> OK, so the answer is yes.
6) MSEL0, MSEL1.... requires related VCCIO = 3.3V, right? So bank 2
VCCIO = 3.3V?
Answer -> MSEL pins should be connected to VCCA. The value of VCCA = 2.5V.
XSHEN - > OK. Can I assign bank 6 VCCIO = 1.8V and CONF_DONE pulled up to 1.8V ?
Can I get this value from datasheet before doing any power analysis job
for choose power supply?
Answer -> Use Early Power Estimator (EPE) tool to estimate the power. For more details and links, refer:
XQSHEN - > I know EPE tools. But the marco in excel is too old to pen. It doesn't work and will stuck computer.
