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Altera_Forum
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8 years ago

QuartusII Prime Pro 16.1/17.1 EMIF(DDR4) Pin Constrain Problem

Hi all, I'm trying to use Quartus II 16.1/17.1 Prime Pro with EMIF to control DDR4. The configuration is descirbed below: FPGA: 10AX066N1F40 DDR4 Config: Single-Rank, x64, Scheme 2 Number of E...
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Altera_Forum
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8 years ago

Hi spdl2001,

thanks for your reply, it's glad to know my understanding is correct!!

However the project I created still having error message when I manually assign RZQ_A/B pins.

But when I create a whole new project, looks like the Blueprint works normally and no similar error occurs. I'll see which step I did wrong in previous project and thanks again for your suggestions.