Quartus Prime Lite - Difficulties with simulation

Hi,

Those threads do not appear to have solutions.

transcript on
if ! {
	file mkdir robot_board_test_iputf_libs
}
if {} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
# ##### Libraries for IPUTF cores 
vlib robot_board_test_iputf_libs/control_internal
vmap control_internal ./robot_board_test_iputf_libs/control_internal
vlib robot_board_test_iputf_libs/modular_adc_0
vmap modular_adc_0 ./robot_board_test_iputf_libs/modular_adc_0
# ##### End libraries for IPUTF cores 
# ##### MIF file copy and HDL compilation commands for IPUTF cores 
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/altera_modular_adc_control.v"             -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/altera_modular_adc_control_avrg_fifo.v"   -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/altera_modular_adc_control_fsm.v"         -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/chsel_code_converter_sw_to_hw.v"          -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/fiftyfivenm_adcblock_primitive_wrapper.v" -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/fiftyfivenm_adcblock_top_wrapper.v"       -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/adc_core_modular_adc_0.v"                 -work modular_adc_0   
vcom "/home/swinchen/quartus/robot_board_test/adc_core/simulation/adc_core.vhd"                                                              
vlog -vlog01compat -work work +incdir+/home/swinchen/quartus/robot_board_test/db {/home/swinchen/quartus/robot_board_test/db/pll_altpll.v}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/slave_spi_interface.vhd}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/robot_board.vhd}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/adc_controller.vhd}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/pll.vhd}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/robot_board_tb.vhd}
vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L fiftyfivenm_ver -L rtl_work -L work -L control_internal -L modular_adc_0 -voptargs="+acc"  robot_board_tb
do /home/swinchen/quartus/robot_board_test/adc_core/simulation/mentor/msim_setup.tcl

Hi,

I tried including the "modular_adc_0" library and get this:

#  Loading modular_adc_0.adc_core_modular_adc_0
#  ** Error: (vsim-3033) /home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/adc_core_modular_adc_0.v(26): Instantiation of 'adc_core_modular_adc_0_control_internal' failed. The design unit was not found.
#     Time: 0 ps  Iteration: 0  Instance: /robot_board_tb/dut/adc_inst/modular_adc_0 File: /home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/adc_core_modular_adc_0.v
#          Searched libraries:
#              /home/swinchen/quartus/robot_board_test/simulation/modelsim/robot_board_test_iputf_libs/modular_adc_0
#              /home/swinchen/quartus/robot_board_test/simulation/modelsim/rtl_work
#  Loading work.slave_spi_interface(rtl)
#  Error loading design
#  End time: 10:57:09 on Feb 09,2018, Elapsed time: 0:00:00
#  Errors: 1, Warnings: 0

I got past the PLL issue

vcom -reportprogress 300 -work work /home/swinchen/quartus/robot_board_test/robot_board_tb.vhd#  Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016#  Start time: 10:25:41 on Feb 09,2018#  vcom -reportprogress 300 -work work /home/swinchen/quartus/robot_board_test/robot_board_tb.vhd #  -- Loading package STANDARD#  -- Loading package TEXTIO#  -- Loading package std_logic_1164#  -- Loading package NUMERIC_STD#  -- Compiling entity robot_board_tb#  -- Compiling architecture rtl of robot_board_tb#  End time: 10:25:41 on Feb 09,2018, Elapsed time: 0:00:00#  Errors: 0, Warnings: 0
vsim work.robot_board_tb#  vsim work.robot_board_tb #  Start time: 10:25:50 on Feb 09,2018#  Loading std.standard#  Loading std.textio(body)#  Loading ieee.std_logic_1164(body)#  Loading ieee.numeric_std(body)#  Loading work.robot_board_tb(rtl)#  Loading altera_mf.altera_mf_components#  Loading work.robot_board(rtl)#  Loading ieee.std_logic_arith(body)#  Loading ieee.std_logic_unsigned(body)#  Loading altera_mf.altera_common_conversion(body)#  Loading altera_mf.altera_device_families(body)#  Loading altera_mf.altsyncram(translated)#  Loading work.pll(syn)#  Loading altera_mf.mf_pllpack(body)#  Loading altera_mf.altpll(behavior)#  Loading altera_mf.mf_cycloneiii_pll(vital_pll)#  Loading altera_mf.mf_cda_mn_cntr(behave)#  Loading altera_mf.mf_cda_scale_cntr(behave)#  Loading work.adc_controller(rtl)#  Loading work.adc_core(rtl)#  ** Warning: (vsim-3473) Component instance "modular_adc_0 : adc_core_modular_adc_0" is not bound.#     Time: 0 ps  Iteration: 0  Instance: /robot_board_tb/dut/adc_inst File: /home/swinchen/quartus/robot_board_test/adc_core/simulation/adc_core.vhd#  Loading work.slave_spi_interface(rtl)#  ** Warning: Design size of 17430 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.#  Expect performance to be adversely affected.#  ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/command_ready, and its initial value is not used.#  Therefore, simulation behavior may occur that is not in compliance with#  the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/command_ready.#  ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/response_valid, and its initial value is not used.#  Therefore, simulation behavior may occur that is not in compliance with#  the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/adc_ram_wr_en.#  ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/response_channel(4), and its initial value is not used.#  Therefore, simulation behavior may occur that is not in compliance with#  the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/adc_ram_wr_chsel(4).#  ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/response_channel(3 downto 0), and its initial value is not used.#  Therefore, simulation behavior may occur that is not in compliance with#  the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/adc_ram_wr_chsel(3 downto 0).#  ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/response_data, and its initial value is not used.#  Therefore, simulation behavior may occur that is not in compliance with#  the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/adc_ram_wr_data.

# ** Warning: (vsim-3473) Component instance "modular_adc_0 : adc_core_modular_adc_0" is not bound.

Hi,

Can you even synthesize the design in Quartus? Perhaps the PLL IP was not generated correctly or you didn't generate simulation model files. Did you make sure that the simulation model is getting compiled in ModelSim?